With the increased demands for high-speed image reading, the recent image reading devices read image data at high-frequency reading clocks such that reducing EMI (Electromagnetic Interference) has been important to be in compliance with the regulations such as FFC (Federal Communications Communication) or VCI (Voluntary Control Council for Information Technology Equipment).
One approach to reduce EMI is to provide SSCG (Spread Spectrum Clock Generator), which flattens the EMI spectrum by modulating the clock frequency in a slow cycle, a narrow range.
FIG. 14 illustrates a circuit structure of a sensor board section of a background image reading device provided with a SSCG circuit 22. The SSCG circuit 22 applies SSCG modulation to a reference clock signal CK output from an oscillator 21 to output a clock signal CKa to a PLL circuit 23. The PLL circuit 23 multiplies the frequency of the clock signal CKa to output a clock signal CKb to a timing generator circuit 24. Based on the clock signal CKb, the timing generator circuit 24 generates a CCD (Charged Coupled Device) drive signal and an AFE (Analog Front End) drive signal, and supplies the CCD drive signal to an AFE 26 through a CCD 25, an emitter follower (EF) circuit 27 and an alternating-current (AC) condenser 28. The timing generator circuit 24 also supplies the AFE drive signal to the AFE 26. The AFE 26 comprises a clamp circuit 29, a sample hold (S/H) circuit 30, a programmable gain amplifier (PGE) circuit 31 and an A/D converter (ADC) 32. Since the clock signal CKb input to the timing generator circuit 24 is generated based on the clock signal CKa to which SSCG modulation is applied, the CCD drive signal and the AFE drive signal are influenced by SSCG modulation.
The SSCG circuit 22, which is provided downstream the oscillator 21, suppresses the electromagnetic interface (EMI) radiation at the peak frequency. As illustrated in FIG. 15, the clock signal CK output from the oscillator 21 has a waveform S1 with the high peak value. When SSCG modulation is applied to the clock signal CK, the frequency values are spread such that the resultant clock signal CKa has a waveform S2 of FIG. 15.
The background image reading device of FIG. 14 with the SSCG circuit 22 has a drawback such that the offset voltage level of the signal output from the CCD 25 changes in synchronization with the SSCG modulated clock signal CKb, as the clock signal CKb is input to the analog timing generator circuit 24. This results in the level of an image signal to periodically change in one main scanning line even when the image signal is obtained from reading an image of the same intensity levels.
More specifically, referring to FIG. 16(b), the frequency of the CCD drive signal fluctuates in a predetermined range around the reference clock frequency, and in a predetermined fluctuation cycle. FIG. 16(a) indicates the change in image pixel level obtained by reading an image of uniform intensities in the main scanning direction for one scanning line, with L indicating the lighter values and D indicating the darker values. The image pixel level fluctuates in synchronization with this fluctuation cycle of the CCD drive signal. Assuming that this fluctuation in image pixel level is repeated for a plurality of lines, the resultant read image would have lines PP, or moiré patterns, due to the difference in image pixel level as illustrated in FIG. 17.
In view of this problem, Japanese Patent Application Publication No. 2008-118366 is provided with a PLL (Phase Locked Loop) loop filter circuit, which extracts a voltage signal in synchronization with modulated frequency of the clock signals. The extracted analog voltage signal is applied, in the inversed phase, to an analog image signal output from the CCD to remove noises that are superimposed over the image signal. The signal used for SSCG modulation has a triangle waveform as illustrated in FIG. 18(a). When this triangle waveform is applied to the oscillating circuit in the PLL circuit, the signal output from the VCO (voltage controlled oscillator) is distorted as the amplitude and the phase of the signal are shifted due to the intensity or linearity of the VCO. This causes the clock signal output from the PLL circuit to have the waveform as indicated by the solid line of FIG. 18(b). In FIG. 18(b), the dotted line indicates the waveform of the clock signal input to the PLL circuit.
As indicated by the solid line of FIG. 18(c), the image signal output from the CCD driven according to this distorted clock signal of FIG. 18(b) has noises that are synchronized with SSCG modulation. The output image signal of FIG. 18(b) further has distortion due to the distorted output signal of the VCO. In FIG. 18(c), the dotted line indicates the waveform of the output signal, which is not distorted.
The circuit disclosed in Japanese Patent Application Publication No. 2008-118366 generates a correction signal having an inversed phase with respect to the phase of the analog image signal output from the CCD based on the clock signal of FIG. 18(b). This correction signal is used to correct the noises that are superimposed on the image signal indicated by the solid line of FIG. 18(c).